1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for testing various kinds of semiconductor devices including a semiconductor integrated circuit and determining whether the tested semiconductor device is a defective (failure) article or not, and more particularly, relates to such a semiconductor device testing apparatus having timing hold function which is capable of conforming the timing at which a test pattern signal is applied to each of terminals of a semiconductor device tinder test and the timing at which a response output signal outputted from each of terminals of the semiconductor device under test is fetched or read in, to a predetermined set value for each terminal.
2. Description of the Related Art
A prior semiconductor device testing apparatus for testing various kinds of semiconductor devices and determining whether the tested semiconductor device is a defective article or not is shown in FIG. 4. Here, for clarity of the description, in FIG. 4 is shown an outline of the construction of a semiconductor integrated circuit testing apparatus for testing a semiconductor integrated circuit (hereinafter, referred to as IC) which is a typical of semiconductor devices and determining whether the tested IC is a defective article or not.
The IC testing apparatus TES comprises, roughly speaking, a controller 11, a pattern generator 12, a timing generator 13, a waveform generating part 14, a logical comparator 15, a driver 16, an analog level comparator (hereinafter referred to as comparator) 17, a failure analysis memory 18, a logical amplitude reference voltage source 21, a comparison reference voltage source 22, and a device power source 23.
The controller 11 is generally constituted by a computer system, in which a test program PM created by a user (programmer) is stored in advance, and the entire IC testing apparatus is controlled in accordance with the test program PM. The controller 11 is connected, via a tester bus BUS, to the pattern generator 12, the timing generator 13, and the like. Although not shown, the logical amplitude reference voltage source 21, the failure analysis memory 18, the logical amplitude reference voltage source 21, the comparison reference voltage source 22, and the device power source 23 are also connected to the controller 11.
First of all, before the testing of an IC is started, various kinds of data are set by the controller 11. After the various kinds of data have been set, the testing of an IC is started. When the controller 11 gives a test starting instruction or command to the pattern generator 12, the pattern generator 12 starts to generate a pattern. The pattern generator 12 supplies test pattern data to the waveform generating part 14, in accordance with the test program PM.
The timing generator 13 generates timing signals (clock pulses) for defining timings of rise and fall of the waveform of a test pattern signal applied to an IC to be tested (IC under test) 19 respectively, and also generates a timing signal (clock pulse) for a strobe pulse which defines a timing of a logical comparison between an expected value pattern signal and a response signal in the logical comparator 15, and the like.
Timings and periods that those timing signals are to be generated are described in the test program PM created by a user, and it is arranged that a test pattern signal can be applied to the IC under test 19 with an operating period and at a timing designed or established by the user to actually operate the IC under test, and whether that operation of the IC under test is normal or not can be tested.
The waveform generating part 14 converts the test pattern data supplied from the pattern generator 12 into a test pattern signal having a real waveform. This test pattern signal is applied to the IC under test 19 via the driver 16 that amplifies the voltage of the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source 21.
A response signal read out from the IC under test 19 is compared with a reference voltage supplied from the comparison reference voltage source 22 in the comparator 17, and it is determined whether or not the response signal has a predetermined logical level, i.e., whether or not the response signal has a predetermined logical H (logical high) voltage or logical L (logical low) voltage. A response signal determined to have the predetermined logical level is sent to the logical comparator 15, where the response signal is compared with an expected value pattern signal outputted from the pattern generator 12, and whether or not the IC under test 19 has outputted a normal response signal is determined.
In case that the IC under test 19 is a memory element, if the response signal does not coincide with the expected value pattern signal, the logical comparator 15 determines that the memory cell having an address of the IC under test 19 from which the response signal has been read out is defective (failure), and generates a failure signal indicating that fact. Usually, when the failure signal is generated, a writing of a failure data (generally logical xe2x80x9c1xe2x80x9d signal) in the failure analysis memory 18 applied to a data input terminal thereof is enabled, and the failure data is stored in an address of the failure analysis memory 18 specified by an address signal being supplied to the failure analysis memory 18 at that time.
The failure analysis memory 18 has its operating rate or speed and its memory capacity equivalent to those of the IC under test 19, and the same address signal as the address signal applied to the IC under test 19 is also applied to this failure analysis memory 18. In addition, the failure analysis memory 18 is initialized prior to the start of a testing. For example, when initialized, the failure analysis memory 18 has data of logical xe2x80x9c0sxe2x80x9d written in all of the addresses thereof. Every time a failure signal indicating that the anti-coincidence is generated from the logical comparator 15 during a testing of the IC under test 19, a failure data of logical xe2x80x9c1xe2x80x9d indicating the failure of a memory cell is written in the same address of the failure analysis memory 18 as that of the memory cell of the IC under test 19 from which that anti-coincidence has occurred.
On the contrary, when the response signal coincides with the expected value pattern signal, the logical comparator 15 determines that the memory cell having an address of the IC under test 19 from which the response signal has been read out is not defective (pass), and generates a pass signal indicating that fact. Usually, this pass signal is not stored in the failure analysis memory 18.
After the testing has been completed, the failure data stored in the failure analysis memory 18 are read out therefrom into a failure relief analyzer not shown, and it is determined, for example, whether a relief or repair of failure memory cells of the tested IC is possible or not.
Further, in FIG. 4, the block diagram is depicted such that the test pattern signal outputted from the driver 16 is applied to only one input terminal of the IC under test 19, and that a response signal from one output terminal of the IC under test 19 is supplied to the comparator 17. However, the number of drivers 16 provided is actually equal to the number of input terminals of the IC under test 19, for example 512, and the number of comparators 17 provided is also equal to the number of output terminals of the IC under test 19 (since the number of input terminals provided is usually equal to the number of output terminals, the number of comparators 17 provided is equal to the number of drivers 16 provided). In addition, although the input terminals of the IC under test 19 are depicted, in FIG. 4, as separate terminals from the output terminals of the IC under test 19, there are many cases in general that each terminal of the IC under test 19 is used in common as both the input terminal and the output terminal.
The IC under test 19 is mounted on an IC socket of a test head (not shown) constructed separately from the IC testing apparatus proper. Usually, a member called xe2x80x9cperformance boardxe2x80x9d is mounted on the upper portion of the test head, and a predetermined number of IC sockets are mounted on the performance board. Accordingly, the IC under test 19 will be mounted on associated one of the IC sockets. In addition, a board (printed board) (hereinafter, referred to as pin card) called xe2x80x9cpin cardxe2x80x9d in this technical field is accommodated inside the test head. Usually, a circuit including the waveform generating part 14, the driver 16 and the comparator 17 of the IC testing apparatus TES is formed on this pin card. There are many cases that the pin card is prepared for each terminal (pin) of the IC under test 19, and is arranged such that when a trouble or failure occurs in any pin card, it is exchangeable for a non-defective pin card. In general, the test head is mounted on a test section of an IC transporting and handling apparatus called handler in this technical field, and is electrically connected to the IC testing apparatus proper by signal transmission means such as a cable, an optical fiber or the like.
FIG. 5 shows an example of the circuit configuration of a pin card. A pin card PCAD shown in FIG. 5 is one for input terminal connected to an input terminal of the IC under test 19, and includes the waveform generating part 14 described above, the driver 16 described above, and a register RG1 to which a delay correcting data is transferred from the controller 11. The test pattern signal outputted from the waveform generating part 14 is applied to one of the input terminals of the IC under test 19 through a test pattern supply path via the driver 16. Although FIG. 5 shows two pin cards PCAD, in reality there are provided, as mentioned above, one pin card PCAD shown in FIG. 5 is connected to each of the all input terminals of the IC under test 19. That is, the same number of pin cards corresponds to the number of input terminals of the IC under test 19 are housed in the test head.
Moreover, each pin card PCAD further includes a variable delay element DY1 provided between the waveform generating part 14 and the driver 16. A delay correcting data is given to the variable delay element DY1 from the register RG1 to adjust the delay time inherent to each pin card PCAD so that a test pattern signal outputted from the waveform generating part 14 can be applied to one of the input terminals of the IC under test 19 in phase with other test pattern signals applied to other input terminals thereof. Such adjustment is generally called xe2x80x9cskew adjustmentxe2x80x9d in this technical field.
There are various kinds of skew adjustment methods. As an example, a reference pin card used as a reference timing is selected among a plurality of pin cards PCAD. Then, a difference of phase between a signal outputted from the reference pin card and a signal outputted from a pin card to be calibrated is found, and finds a delay time for the variable delay element DY1 by which the found phase difference becomes zero (0). Thereafter, the found delay time is fetched in and stored in a delay correcting data storage 11A in a controller 11 as delay correcting data P1, P2, . . . . At the start of a testing, those delay correcting data P1, P2, P3, . . . are transferred from the controller 11 to registers RG1 provided in respective pin cards PCAD so that delay times of corresponding variable delay elements DY1 are set through the associated registers RG1, respectively. After that, the testing is started.
FIG. 6 shows another example of the circuit configuration of a pin card. A pin card PCAD shown in FIG. 6 is one for output terminal connected to an output terminal of the IC under test 19, and includes the above-described comparator 17 to which an response signal outputted from one of the output terminals of the IC under test 19 is supplied, a signal read circuit DF provided at the subsequent stage to the comparator 17, and a register RG2 to which a delay correcting data is transferred from the controller 11. A strobe pulse STB is applied to the signal read circuit DF from the timing generator 13 to fetch or read a logical signal being outputted from the comparator 17 in the signal read circuit DF. The signal read circuit DF may be constructed by D-type flip-flop, for example.
Each pin card PCAD shown in FIG. 6 further includes a variable delay element DY2 inserted in a strobe pulse supply path provided for the purpose of supplying a strobe pulse STB from the timing generator 13 to the signal read circuit DF. In other words, through this strobe pulse supply path a strobe pulse STB from the timing generator 13 passes to the signal read circuit DF. A delay correcting data is given to the variable delay element DY2 from the register RG2 to adjust the delay time of the variable delay element DY2 so that the timing of a strobe pulse applied to the signal read circuit DF coincides with the reference timing.
The delay time of each of the pin cards PCAD is different from one another. Therefore, delay correcting data for correcting such unevenness of the delay times are previously stored in the controller 11, and each time a testing is started, the stored delay correcting data are transferred from the controller 11 to the corresponding registers RG2 provided in the respective pin cards PCAD to adjust the delay times of the variable delay elements DY2 by use of the delay correcting data set in the registers RG2 so that the timings of the strobe pulses STB applied to the signal read circuit DF can be in accord with one another. Although FIG. 6 shows two pin cards PCAD, in reality there are provided, as mentioned above, one pin card PCAD shown in FIG. 6 is connected to each of the all output terminals of the IC under test 19. That is, the same number of pin cards corresponds to the number of output terminals of the IC under test 19 are housed in the test head.
FIG. 7 shows still another example of the circuit configuration of a pin card. A pin card PCAD shown in FIG. 7 is one for both of input and output terminals connected to an input/output terminal (I/O terminal) of the IC under test 19, and is a combination of the circuit configurations of the pin cards mentioned above and shown in FIGS. 5 and 6. Accordingly, the pin card PCAD shown in FIG. 7 is constituted by the waveform generating part 14, the driver 16, the variable delay element DY1, the register RG1 for setting the delay time of the delay element DY1, the comparator 17, the signal read circuit DF, the variable delay element DY2, and the register RG2 for setting the delay time of the delay element DY2. In the register RG1 is set a delay correcting data for the test pattern supply path from the controller 11, and in the register RG2 is set a delay correcting data for the strobe pulse supply path from the controller 11 so that the timing of a test pattern signal propagating through the test pattern supply path and the timing of a strobe pulse propagating through the strobe pulse supply path can be in accord with those of other test pattern signals and those of other strobe pulses, respectively. In general, the pin card of this type is mostly used.
Afore-mentioned delay correcting data are obtained by mounting each pin card PCAD on a predetermined location within the IC testing apparatus TES and by actually operating the IC testing apparatus TES to measure the propagation delay time of the test pattern signal and the propagation delay time of the strobe pulse for each pin card. The measurement results are stored in the delay correcting data storage 11A such as, for example, a hard disk provided in the controller 11.
At the start of the testing, the controller 11 transfers the delay correcting data stored in its delay correcting data storage 11A to the registers RG1 and/or RG2 provided in each of the pin cards PCAD, thereby to set the signal propagation delay times of each pin card, and thereafter the testing is started.
As mentioned above, the prior IC testing apparatus is constructed such that the delay correcting data are previously measured and stored in the controller 11, and at the start of a testing, the stored delay correcting data are transferred from the controller 11 to the registers RG1 and/or RG2 provided in each pin card, thereby to set the delay times of the variable delay elements DY1 and/or DY2. Accordingly, if a pin card PCAD should be in trouble or failure during the testing and this trouble pin card has been replaced with another one, the delay correcting data for the new pin card PCAD must be newly measured once more. To measure the delay correcting data for the new pin card PCAD once more results in the actual operation of the IC testing apparatus TES as stated above, which takes a long time. As a result, there is a drawback in the prior IC testing apparatus that the interruption time of the testing becomes long.
In other words, since an IC testing apparatus is very expensive, if such an expensive apparatus should be stopped for a long time, the operating or running efficiency of the IC testing apparatus is decreased, which results in a drawback that the cost required for the testing is increased.
In addition, as another drawback, there is a possibility that the testing is started again with a new pin card PCAD substituted for the trouble pin card without measuring the delay correcting data for the new pin card. In this case, a delay correcting data transferred from the controller 11 to the new pin card is not data for the new pin card (is data for the former trouble pin card replaced by the new pin card). Accordingly, the delay time of the variable delay element is erroneously set, and an incorrect test result is obtained, resulting in a problem in reliability.
It is a first object of the present invention to provide a semiconductor device testing apparatus having timing hold function which is capable of decreasing a waiting time until a testing is re-started even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced.
It is a second object of the present invention to provide a semiconductor device testing apparatus having timing hold function which has no possibility that in case a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced, a delay correcting data for the former pin card replaced by a new pin card is inadvertently used.
In order to accomplish the aforesaid objects, there is provided, in a first aspect of the present invention, a semiconductor device testing apparatus comprising: a test pattern supply path through which a test pattern signal is supplied to a semiconductor device under test; a variable delay element for adjusting the signal propagation delay time of said test pattern supply path; a register for setting a delay time of said variable delay element; a non-volatile memory; delay correcting data setting means for causing delay correcting data to be stored in said non-volatile memory, said delay correcting data correcting the signal propagation delay time of said test pattern supply path to a prescribed value; and data transfer means for causing the delay correcting data stored in said non-volatile memory to be transferred to said register.
In a first preferred embodiment, the test pattern supply path, the variable delay element, the register and the non-volatile memory are provided on a board called pin card.
The delay correcting data is a difference value between the signal propagation delay time of said test pattern supply path and said prescribed value. Also, the signal propagation delay time of the test pattern supply path is measured before the board is mounted in the semiconductor device testing apparatus.
The delay correcting data stored in said non-volatile memory is transferred to said register by that a controller for controlling the operation of the semiconductor device testing apparatus outputs a transfer instruction of delay correcting data to the non-volatile memory in the initialization setting operation thereof at the start of a testing, thereby to calibrate the signal propagation delay time of said test pattern supply path to the prescribed value.
As a first modification, the testing apparatus may be arranged such that a circuit configuration constituted by said test pattern supply path, said variable delay element, said register and said non-volatile memory is provided as many as plural channels on a board called pin card, and delay correcting data for correcting the signal propagation delay time of each of the test pattern supply paths to said prescribed value is stored in corresponding one of the non-volatile memories.
As a second modification, the testing apparatus may be arranged such that a circuit configuration constituted by said test pattern supply path, said variable delay element and said register is provided as many as plural channels on a board called pin card as well as said non-volatile memory is used in common to the respective test pattern supply paths in the plural channels, and delay correcting data for correcting the signal propagation delay time of each of the test pattern supply paths to said prescribed value is stored in said non-volatile memory.
In a second aspect of the present invention, there is provided a semiconductor device testing apparatus comprising: a signal read circuit for reading therein a logical value of a response signal outputted from a semiconductor device under test; a strobe pulse supply path through which a strobe pulse is supplied to said signal read circuit, said strobe pulse giving to said signal read circuit a timing at which the signal read circuit reads therein the logical value; a variable delay element for adjusting the signal propagation delay time of said strobe pulse supply path; a register for setting a delay time of said variable delay element; a non-volatile memory; delay correcting data setting means for causing delay correcting data to be stored in said non-volatile memory, said delay correcting data correcting the signal propagation delay time of said strobe pulse supply path to a prescribed value; and data transfer means for causing the delay correcting data stored in said non-volatile memory to be transferred to said register.
In a second preferred embodiment, said signal read circuit, said strobe pulse supply path, said variable delay element, said register and said non-volatile memory are provided on a board called pin card.
The delay correcting data is a difference value between the signal propagation delay time of said strobe pulse supply path and said prescribed value. Also, said signal propagation delay time of said strobe pulse supply path is measured before said board is mounted in the semiconductor device testing apparatus.
The delay correcting data stored in said non-volatile memory is transferred to said register by that a controller for controlling the operation of the semiconductor device testing apparatus outputs a transfer instruction of delay correcting data to the non-volatile memory in the initialization setting operation thereof at the start of a testing, thereby to calibrate the signal propagation delay time of said strobe pulse supply path to the prescribed value.
As a first modification, the testing apparatus may be arranged such that a circuit configuration constituted by said signal read circuit, said strobe pulse supply path, said variable delay element, said register and said non-volatile memory is provided as many as plural channels on a board called pin card, and delay correcting data for correcting the signal propagation delay time of each of the strobe pulse supply paths to said prescribed value is stored in corresponding one of the non-volatile memories.
As a second modification, the testing apparatus may be arranged such that a circuit configuration constituted by said signal read circuit, said strobe pulse supply path, said variable delay element and said register is provided as many as plural channels on a board called pin card as well as said non-volatile memory is used in common to the respective strobe pulse supply paths in the plural channels, and delay correcting data for correcting the signal propagation delay time of each of the strobe pulse supply paths to said prescribed value is stored in said non-volatile memory.
In a third aspect of the present invention, there is provided a semiconductor device testing apparatus comprising: a test pattern supply path through which a test pattern signal is supplied to a semiconductor device under test; a first variable delay element for adjusting the signal propagation delay time of said test pattern supply path; a first register for setting a delay time of said first variable delay element, a first non-volatile memory; a signal read circuit for reading therein a logical value of a response signal outputted from a semiconductor device under test; a strobe pulse supply path through which a strobe pulse is supplied to said signal read circuit, said strobe pulse giving to said signal read circuit a timing at which the signal read circuit reads therein the logical value; a second variable delay element for adjusting the signal propagation delay time of said strobe pulse supply path; a second register for setting a delay time of said second variable delay element; a second non-volatile memory; delay correcting data setting means for causing first delay correcting data to be stored in said first non-volatile memory, said first delay correcting data correcting the signal propagation delay time of said test pattern supply path to a prescribed value as well as for causing second delay correcting data to be stored in said second non-volatile memory, said second delay correcting data correcting the signal propagation delay time of said strobe pulse supply path to a prescribed value; and data transfer means for causing the first delay correcting data stored in said first non-volatile memory to be transferred to said first register as well as for causing the second delay correcting data stored in said second non-volatile memory to be transferred to said second register.
In a third preferred embodiment, said test pattern supply path, said first and second variable delay elements, said first and second registers, said signal read circuit, said strobe pulse supply path, and said first and second non-volatile memories are provided on a board called pin card.
The first delay correcting data is a difference value between the signal propagation delay time of said test pattern supply path and said prescribed value, and said second delay correcting data is a difference value between the signal propagation delay time of said strobe pulse supply path and said prescribed value.
The signal propagation delay time of said test pattern supply path and said signal propagation delay time of said strobe pulse supply path are measured before said board is mounted in the semiconductor device testing apparatus.
The first and second delay correcting data stored respectively in said first and second non-volatile memories are transferred to said first and second registers respectively by that a controller for controlling the operation of the semiconductor device testing apparatus outputs a transfer instruction of delay correcting data to the first and second non-volatile memories in the initialization setting operation thereof at the start of a testing, thereby to calibrate the signal propagation delay times of said strobe pulse supply path and said strobe pulse supply path to the respective prescribed values.
As a first modification, the testing apparatus may be arranged such that in place of the first and second non-volatile memories, only one nonvolatile memory is provided, and both of the first and second delay correcting data are stored in the non-volatile memory.
In this first modification, said test pattern supply path, said first and second variable delay elements, said first and second registers, said signal read circuit, said strobe pulse supply path, and said non-volatile memory are provided on a board called pin card.
In addition, said first and second delay correcting data stored in said non-volatile memory are transferred to said first and second registers respectively by that a controller for controlling the operation of the semiconductor device testing apparatus outputs a transfer instruction of delay correcting data to the non-volatile memory in the initialization setting operation thereof at the start of a testing, thereby to calibrate the signal propagation delay times of said strobe pulse supply path and said strobe pulse supply path to the respective prescribed values.
As a second modification, the testing apparatus may be arranged such that a circuit configuration constituted by said test pattern supply path, said first variable delay element, said first register and said first non-volatile memory is provided as many as plural channels on a board called pin card, and a circuit configuration constituted by said strobe pulse supply path, said second variable delay element, said second register, said signal read circuit and said second non-volatile memory is provided as many as plural channels on said board, and said first delay correcting data for correcting the signal propagation delay time of each of the test pattern supply paths to the prescribed value and said second delay correcting data for correcting the signal propagation delay time of each of the strobe pulse supply paths to the prescribed value are stored in corresponding one of said first non-volatile memories and corresponding one of said second non-volatile memories respectively.
As a third modification, the testing apparatus may be arranged such that a circuit configuration constituted by said test pattern supply path, said first and second variable delay elements, said first and second registers, said signal read circuit, said strobe pulse supply path, and said non-volatile memory is provided as many as plural channels on a board called pin card, and said first delay correcting data for correcting the signal propagation delay time of the test pattern supply path to the prescribed value and said second delay correcting data for correcting the signal propagation delay time of the strobe pulse supply path to the prescribed value in each channel are stored in the non-volatile memory in the same channel.
As a fourth modification, the testing apparatus may be arranged such that a circuit configuration constituted by said test pattern supply path, said first and second variable delay elements, said first and second registers, said signal read circuit, and said strobe pulse supply path is provided as many as plural channels on a board called pin card, and said non-volatile memory is used in common to the plural channels, and said first delay correcting data for correcting the signal propagation delay time of the test pattern supply path to the prescribed value and said second delay correcting data for correcting the signal propagation delay time of the strobe pulse supply path to the prescribed value in each channel are stored in the non-volatile memory.
According to the semiconductor device testing apparatus having a timing hold function according to the present invention, it is configured such that upon completion of the assembly of a pin card, a signal propagation delay time or times of a test pattern supply path and/or a strobe pulse supply path provided on each pin card is measured in the state of a single pin card, and in order to conform the measured signal propagation delay time or times to a predetermined value, delay correcting data to be set in a variable delay element is found, and the obtained delay correcting data is stored in a non-volatile memory or memories provided on each pin card. Accordingly, at the time point that any trouble or defect occurs in a pin card and even if the trouble pin card is replaced by any new pin card, the delay time of the variable delay element can be set by utilizing the delay correcting data stored in the non-volatile memory in the new pin card. Therefore, the testing can be re-started immediately without measuring the propagation delay time.
In other words, it is not necessary to measure the signal propagation delay time or times of the test pattern supply path and/or the strobe pulse supply path provided in each of the pin cards every time a pin card is replaced. Accordingly, there is obtained a remarkable advantage that the interrupted time duration of the testing can be decreased significantly.
Moreover, in accordance with the semiconductor device testing apparatus according to the present invention, since delay correcting data stored in the non-volatile memory or memories is set in the variable delay element or elements to initialize it without fail when the testing apparatus is started, there is no possibility that an incorrect operation occurs that the testing apparatus operates by using delay correcting data for the former trouble pin card. Consequently, a highly reliable semiconductor device testing apparatus can be provided.